US Patent Issued to Institute of Semiconductors, Chinese Academy of Sciences on Sept. 1 for "Method for fabricating semiconductor structure having enhanced hole linear Rashba spin-orbit coupling effect" (Chinese Inventors)

Posted On: 2026-09-01

ALEXANDRIA, Va., Sept. 1 -- United States Patent no. 12,727,208, issued on Sept. 1, was assigned to Institute of Semiconductors, Chinese Academy of Sciences (Beijing). "Method for fabricating semicon... Read More

US Patent Issued to IDEAL SEMICONDUCTOR DEVICES on Sept. 1 for "Combined charge balance and edge termination surface passivation for a semiconductor device and methods of fabricating the same" (Pennsylvania Inventors)

Posted On: 2026-09-01

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ALEXANDRIA, Va., Sept. 1 -- United States Patent no. 12,727,209, issued on Sept. 1, was assigned to IDEAL SEMICONDUCTOR DEVICES INC. (Bethlehem, Pa.). "Combined charge balance and edge termination su... Read More

US Patent Issued to FUJI ELECTRIC on Sept. 1 for "Semiconductor device" (Japanese Inventor)

Posted On: 2026-09-01

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ALEXANDRIA, Va., Sept. 1 -- United States Patent no. 12,727,210, issued on Sept. 1, was assigned to FUJI ELECTRIC Co. LTD. (Kanagawa, Japan). "Semiconductor device" was invented by Takamasa Ishikawa ... Read More

US Patent Issued to NANYA TECHNOLOGY on Sept. 1 for "Semiconductor device structure with backside pick-up region and method of manufacturing the same" (Taiwanese Inventor)

Posted On: 2026-09-01

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ALEXANDRIA, Va., Sept. 1 -- United States Patent no. 12,727,211, issued on Sept. 1, was assigned to NANYA TECHNOLOGY Corp. (New Taipei City, Taiwan). "Semiconductor device structure with backside pic... Read More

US Patent Issued to ROHM on Sept. 1 for "Semiconductor device with voltage resistant structure" (Japanese Inventors)

Posted On: 2026-09-01

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ALEXANDRIA, Va., Sept. 1 -- United States Patent no. 12,727,212, issued on Sept. 1, was assigned to ROHM Co. LTD. (Kyoto, Japan). "Semiconductor device with voltage resistant structure" was invented ... Read More

US Patent Issued to ChangXin Memory Technologies on Sept. 1 for "Manufacturing method of semiconductor structure with flat isolation layer and semiconductor structure" (Chinese Inventor)

Posted On: 2026-09-01

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ALEXANDRIA, Va., Sept. 1 -- United States Patent no. 12,727,213, issued on Sept. 1, was assigned to ChangXin Memory Technologies Inc. (Hefei, China). "Manufacturing method of semiconductor structure ... Read More

US Patent Issued to Applied Materials on Sept. 1 for "Source drain formation in gate all around transistor" (California Inventors)

Posted On: 2026-09-01

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ALEXANDRIA, Va., Sept. 1 -- United States Patent no. 12,727,214, issued on Sept. 1, was assigned to Applied Materials Inc. (Santa Clara, Calif.). "Source drain formation in gate all around transistor... Read More

US Patent Issued to SAMSUNG ELECTRONICS on Sept. 1 for "Boundary gate structure for diffusion break in 3D-stacked semiconductor device" (New York Inventors)

Posted On: 2026-09-01

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ALEXANDRIA, Va., Sept. 1 -- United States Patent no. 12,727,215, issued on Sept. 1, was assigned to SAMSUNG ELECTRONICS Co. LTD. (Suwon-si, South Korea). "Boundary gate structure for diffusion break ... Read More

US Patent Issued to Taiwan Semiconductor Manufacturing on Sept. 1 for "Transistor protection layers and methods of forming the same" (Taiwanese Inventors)

Posted On: 2026-09-01

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ALEXANDRIA, Va., Sept. 1 -- United States Patent no. 12,727,216, issued on Sept. 1, was assigned to Taiwan Semiconductor Manufacturing Co. Ltd. (Hsinchu, Taiwan). "Transistor protection layers and me... Read More

US Patent Issued to Korea Institute of Science and Technology on Sept. 1 for "Semiconductor device including trench with undercut structure and method for manufacturing the same" (South Korean Inventors)

Posted On: 2026-09-01

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ALEXANDRIA, Va., Sept. 1 -- United States Patent no. 12,727,217, issued on Sept. 1, was assigned to Korea Institute of Science and Technology (Seoul, South Korea). "Semiconductor device including tre... Read More

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US Patent Issued to Institute of Semiconductors, Chinese Academy of Sciences on Sept. 1 for "Method for fabricating semiconductor structure having enhanced hole linear Rashba spin-orbit coupling effect" (Chinese Inventors)

US Patent Issued to IDEAL SEMICONDUCTOR DEVICES on Sept. 1 for "Combined charge balance and edge termination surface passivation for a semiconductor device and methods of fabricating the same" (Pennsylvania Inventors)

US Patent Issued to FUJI ELECTRIC on Sept. 1 for "Semiconductor device" (Japanese Inventor)

US Patent Issued to NANYA TECHNOLOGY on Sept. 1 for "Semiconductor device structure with backside pick-up region and method of manufacturing the same" (Taiwanese Inventor)

US Patent Issued to ROHM on Sept. 1 for "Semiconductor device with voltage resistant structure" (Japanese Inventors)

US Patent Issued to ChangXin Memory Technologies on Sept. 1 for "Manufacturing method of semiconductor structure with flat isolation layer and semiconductor structure" (Chinese Inventor)

US Patent Issued to Applied Materials on Sept. 1 for "Source drain formation in gate all around transistor" (California Inventors)

US Patent Issued to SAMSUNG ELECTRONICS on Sept. 1 for "Boundary gate structure for diffusion break in 3D-stacked semiconductor device" (New York Inventors)

US Patent Issued to Taiwan Semiconductor Manufacturing on Sept. 1 for "Transistor protection layers and methods of forming the same" (Taiwanese Inventors)

US Patent Issued to Korea Institute of Science and Technology on Sept. 1 for "Semiconductor device including trench with undercut structure and method for manufacturing the same" (South Korean Inventors)